Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method

ABSTRACT

The invention relates to a method of manufacturing a semiconductor device ( 10 ) with a semiconductor body ( 1 ) and a substrate ( 2 ) comprising at least one semiconductor element ( 3 ) and provided with at least one connection region ( 4 ) and an overlying stripe-shaped connection conductor ( 5 ) which is connected to the connection region ( 4 ), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer ( 6 ), a hard mask layer ( 7 ), and a second dielectric layer ( 8 ) are deposited on the semiconductor body ( 1 ), where at the location of the connection region ( 4 ) to be formed, a via ( 44 ) is formed in the first dielectric layer ( 6 ) by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned photoresist layer deposited on top of the structure and at the location of the connection conductor ( 6 ) to be formed, a trench ( 55 ) is formed in the second dielectric layer ( 8 ) by means of plasma etching, which via ( 44 ) and trench ( 55 ) are filled with an electrically conducting material in order to form, respectively, the connection region ( 4 ) and the connection conductor ( 5 ), and where before the trench ( 55 ) is formed, the already formed via ( 44 ) is filled with an organic material ( 20 ). According to the invention, the material of the first dielectric layer ( 6 ) and the etch conditions during formation of the via ( 44 ) in the first dielectric layer ( 6 ) by plasma etching are chosen such that during etching the via ( 44 ), said via ( 44 ),said via ( 44 ) is at the same time substantially completely filled with the organic material ( 20 ), which organic material ( 20 ) is formed from organic material already present within the structure and within the plasma. Relevant conditions—apart from the presence of the resist layer during etching and the use therein of a compound of carbon and fluor—relate to the choice of the material of the first (and second) dielectric layer(s)  6,8  and the power during etching of these layers ( 6,8 ).

The invention relates to a method of manufacturing a semiconductordevice with a semiconductor body and a substrate comprising at least onesemiconductor element and provided with at least one connection regionand an overlying stripe-shaped connection conductor which is connectedto the connection region, which connection conductor and connectionregion are both recessed in a dielectric material, where subsequently afirst dielectric layer, a first hard mask layer, and a second dielectriclayer are deposited on the semiconductor body, where at the location ofthe connection region to be formed, a via is formed in the firstdielectric layer by means of plasma etching using a plasma containingcompounds of carbon and fluor, and at the location of the connectionconductor to be formed, a trench is formed in the second dielectriclayer by means of plasma etching and a patterned photoresist layer ispresent on top of the structure during etching, which via and trench arefilled with an electrically conducting material in order to form,respectively, the connection region and the connection conductor, andwhere before the trench is formed, the already formed via is filled withan organic material. Such a method is particularly suitable for themanufacturing of more complex semiconductor devices that aremanufactured in the so-called multi-level or multi-layer technique.

Such a method is known from U.S. Pat. No. 6.362.093, which was publishedon Mar. 26, 2002. Said document describes (see in particular FIG. 2) howon a contact region in a substrate a stack is deposited of a barrierlayer, a first dielectric layer, a hard mask layer, and a seconddielectric layer. On top of this structure a patterned photoresist layeris deposited and a via is formed not only in the first dielectric layerbut also in the second dielectric layer by plasma etching using a plasmacontaining a compound of carbon and fluor. Thereafter (see in particularFIG. 3), the via thus formed is filled with an organic material in theform of a spin-on organic material, and a photoresist layer with adifferent pattern is formed on top of this structure and subsequently atrench is formed in the second dielectric layer by plasma etching. Inthis process the organic material in both the via in the firstdielectric layer and the via in the second dielectric layer is againcompletely removed. Then both the via and the trench are filled with aconducting material. The organic material in the via has a sacrificialfunction in that it protects—in particular the bottom of—the via whileforming the trench by etching.

A disadvantage of such a method is that it is rather complicated as itcomprises several steps for forming the via filled with the sacrificialorganic material; such as inter alia the formation of the via by anetching step and filling it by deposition of a spin-on material.

It is therefore an object of the present invention to avoid the abovedrawbacks and to provide a method that is simple and has fewer steps.

To achieve this, a method of the type described in the opening paragraphis characterized in that the material of the first dielectric layer andthe etch conditions during formation of the via in the first dielectriclayer by plasma etching are chosen such that during etching the via,said via is at the same time substantially completely filled with theorganic material, which organic material is formed from organic materialalready present within the structure and the plasma. The presentinvention is firstly based on the surprising recognition that bothformation of the via by etching and, during the same process, filling itwith organic material is possible provided that in particular for thefirst dielectric material a suitable material is chosen and providedthat the conditions during etching are chosen to be suitable as well.

It appeared that a suitable material for the first dielectric layer is amaterial which contains organic material. Together with the organicmaterial present in the photoresist layer and the carbon-fluor compoundin the plasma, an organic polymer-like material is formed which depositsinto the via during its formation. The organic material in the firstdielectric layer apparently also plays some role, either as a source ofcarbon or as a catalyst. Essential conditions during plasma etching inorder to obtain the results according to the invention are that thepower of the plasma equipment should be between 500 and 2200 Watt. Thusthe method according the invention is quick and simple as only one stepis needed for forming the via by etching and filling it with a(sacrificial) organic material. Finally, an important and surprisingadvantage of the method according to the invention is that it does notresult in damage to the bottom faces of the trench during trenchformation nor to damage to the upper part of the sidewalls of the viaduring said process. In the known method, on the contrary, the use of aspin-on photoresist to form the sacrificial filling of the via resultedin damages of the kind mentioned during the formation of the trench byplasma etching.

For the material of the first dielectric layer an organic polymer may beused or a hybrid material comprising an inorganic material like poroussilicon dioxide comprising also organic material. A suitable example ofthe latter is LKD-5109, available from TSR Corporation. As a polymere.g. a material like SILK (which is a trademark of the Dow ChemicalCompany) may be used. A particular advantage of these materials is thatthey have lower dielectric constants than pure inorganic silicon dioxideand thus the capacitance of a structure in which two conductors areseparated by said materials is reduced, thus favoring high frequencybehavior.

In a favorable embodiment of a method according to the invention, thevia is formed after deposition of the first dielectric layer and thefirst hard mask layer, and after forming an opening in the first hardmask layer but before deposition of the second dielectric layer andafter forming the via by etching and simultaneously filling said) viawith organic material, the second dielectric layer and the second hardmask layer are deposited. In this method the thickness of the via isminimal as it only comprises the first dielectric layer. It has beenfound that in such a case where the via is relatively thin, it is moreeasy to form the via and at the same time fill it with organic material.In this embodiment the central part of the second dielectric layer infact fulfills the function of a sacrificial material during formation ofthe trench by etching.

In another embodiment, the via is formed after deposition of the seconddielectric layer and the via is also formed in the second dielectriclayer. Preferably for the second dielectric material the same kind ofmaterial is chosen as for the first dielectric material in order tocompletely fill the via comprising in this case both dielectric layers.

Preferably after the deposition of the second dielectric layer, a secondhard mask layer is deposited on top thereof and the via is formed afterforming an opening in the second hard mask layer using a photoresistmask to form said opening by means of etching.

Preferably the trench is formed after forming the via and at the sametime filling it with the organic material using another photoresist maskformed on top of the second hard mask layer and another etching process.

Providing the trench with a larger width than the width of the via hasthe advantage that the connection conductor formed within the trench hasa low resistance and is more easily aligned with the connection regionformed within the via.

Preferably copper is chosen for the electrically conducting material ofthe connection region and the connection conductor because of itssuperior conductivity. In that case, before the deposition of the firstdielectric layer a barrier layer for copper is deposited on thesemiconductor body. Such a layer may be made of tantalum or tantalumnitride. It protects the underlying semiconductor body againstcontamination by copper.

In another variant, after formation of the via and the trench but beforedeposition of copper, a thin polymer layer is formed on the walls of thevia and the trench. This layer may be formed in a similar way as thesacrificial organic material in the via However, the conditions are nowchosen such that only a thin polymer layer is deposited. Afterwards abarrier layer for copper is deposited on the bottom of the via and onthe sidewalls of the via and the trench. Thanks to the presence of thepolymer layer, the walls of the via and of the trench become smooth andthus a smooth and reliable formation of a barrier layer thereon ispossible. Moreover, it appeared that in the case of a barrier layercomprising tantalum, the resistance of the tantalum layer is lower thanin the case of the a tantalum layer deposited without the presence ofthe polymer layer.

Preferably, the etching/filling of the via is carried out using, as thecompound of carbon and fluor, a compound which is chosen from the groupcomprising CH₂F₂ and CH₃F. Apparently, the chemistry involved in thesecases is rather effective, as the results obtained were very satisfying.The remainder of the organic material formed and of the resist presentare finally, i.e. at the end of the process, and completely removed by awet or dry etch process, a so-called stripping process.

The invention also covers a semiconductor device obtained by means of amethod according to the invention.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiment(s) described hereinafter, tobe read in conjunction with the drawing, in which

FIGS. 1 through 6 are sectional views of a semiconductor device atvarious stages in the manufacture of the device by means of a method inaccordance with the invention, and

FIGS. 7 through 11 are sectional views of a semiconductor device atvarious stages in the manufacture of the device by means of amodification of the method in accordance with the invention.

The figures are diagrammatic and not drawn to scale, the dimensions inthe thickness direction being particularly exaggerated for greaterclarity. Corresponding parts are generally given the same referencenumerals and the same hatching in the various figures.

FIGS. 1 through 6 are sectional views of a semiconductor device atvarious stages in the manufacture of the device by means of a method inaccordance with the invention. The device 10 (see FIG. 1) comprises asemiconductor body 1 which, in this case, is made of silicon but whichmay alternatively be made of another suitable semiconductor material. Asa basis for the body 1 use is made of a p-type silicon substrate 2 inwhich a semiconductor element 3 is formed, e.g. a p-type region forminga source, drain, base, emitter or the like of a transistor or a part ofa diode. In particular in the multi-layer/multi-level technique, element3 will be formed by a conductor of a lower level of the device 10. Thesemiconductor element 3 then is formed at another location within thesemiconductor body 1.

The method according to the invention continues in this example with thedeposition of a barrier layer 12 of tantalum nitride. Subsequently, afirst dielectric layer 6 of porous silicon dioxide containing organicmaterial, here LKD-5109 available from TSR Corporation, is deposited ina thickness of 200 to 300 nm. On top of the first dielectric layer 6 a50 nm thick hard mask layer 7 is deposited, which in this example ismade of silicon carbide (SiC). A photoresist layer 11 is depositedthereon and patterned, which photoresist layer is mainly made ofmethacrylate and is 450 nm thick. The opening in the resist layer 11 iscircular here and has a diameter of 250 to 350 nm, which corresponds tothe diameter of the connection region 4 to be formed.

Subsequently (see FIG. 2), the device 10 is treated in a plasma etchingmachine (not shown in the drawing) the plasma of which contains acompound of carbon and fluor, here CH₃F. The plasma etching treatment iscarried out at a power in the range of 500 to 2200 Watt. First anopening is formed in the first hard mask layer 7. And, according to theinvention, at the same time a hole 44 is formed in the first dielectriclayer 6 which, at the same time, is filled with an organic material 20.Thus, the method according to the invention is very efficient.

Hereafter (see FIG. 3), on the device 10, a second dielectric layer 8 isdeposited, in this case, of the same material as that of the firstdielectric layer and having a thickness of 200 to 300 nm. On top thereofa second hard mask layer 9 is deposited, here also of silicon carbide(SiC), having a thickness of 50 nm. Thereon, a fotoresist layer 111mainly of methacrylate and 450 nm thick is deposited and patternedaccording to the length and width, here 200 to 400 nm, of the connectionconductor 5 to be formed.

Then (see FIG. 4) the second hard mask layer 9 is provided with anopening, corresponding to the opening in the fotoresist layer 111, bymeans of etching in a plasma comprising CH₂F₂ and/or CH₃F, here CH₃F.

Subsequently (see FIG. 5), a trench 55 is formed by continued etchinguntil the organic material 20 (see FIG. 6) is reached. From that momentetching is continued by means of plasma etching with a plasma comprisinga mixture of N₂/O₂. Now (see FIG. 6), the organic material 20 in the via44 is removed until the bottom of the via 44 is reached. At the sametime the (remainder of) resist layer 111 is removed. An importantadvantage of the method according to the invention is that the“shoulders” formed at the interface between the via 44 and the trench 55are not damaged. This is quite contrary to the known method in whichsuch damage occurs. In this example a thin polymer layer—not shown inthe Figure—is deposited on the walls of the via 44. Thereafter a furtherbarrier layer, preferably of tantalum,—also not shown in the drawing—isdeposited on said polymer layer. Then the via 44 and the trench 55 arefilled, in this example, with copper to form the connection region 4 andthe connection conductor 5, the upper level thereof being represented inFIG. 6 by means of a dashed line 4,5. The copper is deposited in thisexample by an electroplating technique.

The process will now be continued in a way similar to the knownprocesses in order to complete the device 10. The steps involved are notillustrated in the drawing. Usual process steps are a CMP process andpossibly the process steps involved in the formation of furtherconnection regions and connection conductors which are recessed in adielectric, followed by a CMP process. Then for example a siliconcarbide layer is deposited in which openings are made in which aconnection metal like aluminum is deposited, e.g. as a blanket layer,followed by photolithography and etching. Finally, individual devices 10may be obtained by means of a separation process like sawing.

Below, a second example, which is modification of the first example, isgiven of a method according to the invention.

FIGS. 7 through 11 are sectional views of a semiconductor device atvarious stages in the manufacture of the device by means of amodification of the method in accordance with the invention. The methodaccording to the invention applied in this example shows somesimilarities with that of the first example and therefore we refer hereto the description of the first example for certain details. Here, onlythe predominant differences will be briefly discussed.

As a basis (see FIG. 7) for the manufacture of device 10 use is made ofa semiconductor body 1 which again comprises a silicon substrate 2 witha semiconductor element 3 on top of which a barrier layer 12, a firstdielectric layer 6 and a first hard mask layer 7 are deposited. Now, ontop thereof a second dielectric layer 8, here of the same material asthe first dielectric layer 6 is deposited and on top of said seconddielectric layer a second hard mask layer 9 is deposited which isprovided with a patterned resist layer 11.

Then (see FIG. 8) an opening is etched in the second hard mask layer 9and subsequently a hole 44 is etched throughout the structure 10 untilthe barrier layer 12 is reached. At the same time, the hole 44 thusformed is filled with an organic material 20. The hole 44 has the sizeof the desired connection region 4 to be formed.

Subsequently (see FIG. 9) a further patterned resist layer 111 isdeposited on top of the second hard mask layer 9 having the width andthe length of the desired connection conductor 5 to be formed. Then (seeFIG. 10) an etching operation is started in which both the organicmaterial 20 and the unprotected parts of the second hard mask layer 9and the second dielectric layer 8 are etched away. After reaching thelevel of the via 44 etching is continued in a similar way as in thefirst example such that the remainder of the organic material 20 and the(remainder) of the resist 111 is removed. Finally, the situation (seeFIG. 11) is reached where both the via 44 and the trench 55 arecompletely formed. Both are again filled with copper 4,5, indicated bythe dashed line, to form connection region 4 and connection conductor 5.

It will be obvious that the invention is not limited to the examplesdescribed herein, and that within the scope of the invention manyvariations and modifications are possible to those skilled in the art.

For example, semiconductor devices having a different geometry and sizemay be made. The substrate may comprise an insulating material likeglass and the semiconductor body may then be formed e.g. by a so-calledsubstrate transfer technique. The dielectric layers may comprise otherso-called low-K materials.

It is also to be noted that the device to be made may comprise furtheractive and/or passive semiconductor elements or electronic elements likea (large number of) diodes, transistors and/or resistors and/orcapacitors, e.g. in the form of an IC (=Integrated Circuit).

1. Method of manufacturing a semiconductor device with a semiconductorbody and a substrate comprising at least one semiconductor element andprovided with at least one connection region and an overlyingstripe-shaped connection conductor connected to the connection regionwhich connection conductor and connection region are both recessed in adielectric material, where subsequently a first dielectric layer, a hardmask layer, and a second dielectric layer are deposited on thesemiconductor body, where at the location of the connection region to beformed, a via is formed in the first dielectric layer by plasma etchingusing a plasma containing a compound of carbon and fluorine, and in thepresence of a patterned photoresist layer deposited on top of theconnection region and at the location of the connection conductor to beformed, a trench is formed in the second dielectric layer by plasmaetching, which via and trench are filled with an electrically conductingmaterial in order to form, respectively, the connection region and theconnection conductor, and where before the trench is formed, the alreadyformed via is filled with an organic material, characterized in that thematerial of the first dielectric layer and the etch conditions duringformation of the via in the first dielectric layer by plasma etching arechosen such that during etching the via, said via is at the same timesubstantially completely filled with the organic material, the organicmaterial being formed from organic material already present within thealready formed via and within the plasma, wherein the organic materialin the via acts as a sacrificial material thereby protecting the viaduring plasma etching and during trench formation, resulting in enhanceddimensional integrity of the via and trench structure.
 2. Methodaccording to claim 1, characterized in that for the material of thefirst dielectric layer a material is chosen which contains organicmaterial.
 3. Method according to claim 2, characterized in that for thematerial of the first dielectric layer a polymer is chosen.
 4. Methodaccording to claim 2, characterized in that for the material of thefirst dielectric layer a material is chosen comprising porous silicondioxide comprising organic material.
 5. Method according to claim 1,characterized in that during plasma etching the via, the power settingis chosen between 500 and 2200 Watts.
 6. Method-according to claim 1,characterized in that the via is formed after deposition of the firstdielectric layer and the first hard mask layer, and after forming anopening in the first hard mask layer and after forming the via byetching and simultaneously filling said via with organic material, thesecond dielectric layer and the second hard mask layer are deposited. 7.Method according to claim 1, characterized in that the via is formedafter deposition of the second dielectric layer, and the via is formedalso in the second dielectric layer.
 8. Method according to claim 1,characterized in that the trench is formed after forming the via and atthe same time filling it with the organic material using a photoresistmask.
 9. Method according to claim 8, characterized in that the width ofthe trench is chosen to be larger than the width of the via.
 10. Methodaccording to claim 1, characterized in that copper is chosen forteelectrically conducting material.
 11. Method according to claim 10,characterized in that before the deposition of the first dielectriclayer, a barrier layer for copper is deposited on the semiconductorbody.
 12. Method according to claim 10, characterized in that afterformation of the via and the trench but before deposition of the copper,a thin polymer layer is formed on the walls of the via and the trenchand a further barrier layer for copper is deposited on the bottom of thevia and on the side walls of the via and the trench.
 13. Methodaccording to claim 1, characterized in that a further hard mask layer isdeposited on top of the second dielectric layer.
 14. Method according toclaim 1, characterized in that as the compound of carbon and fluor, acompound is chosen from the group comprising CH₂F₂and CH₃F. 15.Semiconductor device obtained with a method according to claim 1.